Kota Shiba (柴 康太), Ph.D. Senior Engineer at TSMC IEEE MemberIEEE Solid-State Circuits Society MemberIEEE Circuits and Systems Society Member kshiba@ieee.org LinkedIn Google Scholar Researchmap Research Interests 3D System Integration High-speed Low-power Wireless Interface Efficient Deep Learning Accelerator Efficient Computation-in-memory (CIM) Low-power SRAM Work Experience 4/2023 – PresentSenior Engineer, TSMC 10/2021 – 3/2023ACT-X Researcher, Japan Science and Technology Agency (JST) 4/2021 – 3/2023Research Fellow (DC2), Japan Society for the Promotion of Science (JSPS) 10/2020 – 3/2021School of Engineering, The University of Tokyo Research Assistant (SEUT-RA), The University of Tokyo 4/2018 – 3/2023Internship role, dricos, Inc. Education 4/2020 – 3/2023Ph.D., Department of Electrical Engineering and Information Systems, The University of Tokyo, Tokyo, Japan 4/2018 – 3/2020M.S., Department of Electronics and Electrical Engineering, Keio University, Yokohama, Japan 4/2014 – 3/2018B.S., Department of Electronics and Electrical Engineering, Keio University, Yokohama, Japan Achievement Journal Paper: 11(with JSSC, 2x TCAS-I, 3x SSC-L) Conference Presentation: 24(with VLSIC, 2x A-SSCC, 2x ESSCIRC, 2x Hot Chips, 2x ISCAS) Awards: 3 Funding: 2(with JSPS DC2, JST ACT-X) Paper Reviews: 3(with TCAS-I, 2x TCAS-II)