Kota Shiba (柴 康太), Ph.D.

Senior Engineer at TSMC

IEEE Member
IEEE Solid-State Circuits Society Member
IEEE Circuits and Systems Society Member

kshiba@ieee.org

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Research Interests

3D System Integration

High-speed Low-power Wireless Interface

Efficient Deep Learning Accelerator

Efficient Computation-in-memory (CIM)

Low-power SRAM

Work Experience

4/2023 – Present
Senior Engineer, TSMC

10/2021 – 3/2023
ACT-X Researcher, Japan Science and Technology Agency (JST)

4/2021 – 3/2023
Research Fellow (DC2), Japan Society for the Promotion of Science (JSPS)

10/2020 – 3/2021
School of Engineering, The University of Tokyo Research Assistant (SEUT-RA), The University of Tokyo

4/2018 – 3/2023
Internship role, dricos, Inc.

Education

4/2020 – 3/2023
Ph.D., Department of Electrical Engineering and Information Systems, The University of Tokyo, Tokyo, Japan

4/2018 – 3/2020
M.S., Department of Electronics and Electrical Engineering, Keio University, Yokohama, Japan

4/2014 – 3/2018
B.S., Department of Electronics and Electrical Engineering, Keio University, Yokohama, Japan

Achievement

Journal Paper: 11
(with JSSC, 2x TCAS-I, 3x SSC-L)

Conference Presentation: 24
(with VLSIC, 2x A-SSCC, 2x ESSCIRC, 2x Hot Chips, 2x ISCAS)

Awards: 3

Funding: 2
(with JSPS DC2, JST ACT-X)

Paper Reviews: 3
(with TCAS-I, 2x TCAS-II)