Publication

Journal Paper/学術論文誌

1. R. Sumikawa, A. Kosuge, Y.-C. Hsu, K. Shiba, M. Hamada, and T. Kuroda,
   “A 183.4-nJ/Inference 152.8-μW 35-Voice Commands Recognition Wired-Logic Processor Using Algorithm-Circuit Co-Optimization Technique,”
   IEEE Solid-State Circuits Letters (SSC-L), vol. 7, pp. 22-25, 2024.
   [DOI] 10.1109/LSSC.2023.3334625
2. K. Shiba, M. Okada, A. Kosuge, M. Hamada, and T. Kuroda,
   “Polyomino: A 3D-SRAM-Centric Accelerator for Randomly Pruned Matrix Multiplication With Simple Reordering Algorithm and Efficient Compression Format in 180-nm CMOS,”
   IEEE Transactions on Circuits and Systems-I: Regular Papers (TCAS-I), vol. 70, no. 9, pp. 3440-3450, Sep. 2023.
   [DOI] 10.1109/TCSI.2023.3268772
   Special Issue on the IEEE International NEWCAS Conference 2022
3. K. Shiba, A. Kosuge, M. Hamada, and T. Kuroda,
   “Crosstalk Analysis and Countermeasures of High-Bandwidth 3D-Stacked Memory Using Multi-Hop Inductive Coupling Interface,”
   IEICE Transactions on Electronics, vol. E106-C, no. 7, pp. 391-394, July 2023.
   [DOI] 10.1587/transele.2022CDS0001
4. K. Shiba, M. Okada, A. Kosuge, M. Hamada, and T. Kuroda,
   “A 7-nm FinFET 1.2-TB/s/mm² 3D-Stacked SRAM Module with 0.7-pJ/b Inductive Coupling Interface Using Over-SRAM Coil and Manchester-encoded Synchronous Transceiver,”
   IEEE Journal of Solid-State Circuits (JSSC), vol. 58, no. 7, pp. 2075-2086, July 2023.
   [DOI] 10.1109/JSSC.2022.3224421
5. K. Shiba, M. Okada, A. Kosuge, M. Hamada, and T. Kuroda,
   “A 12.8-Gb/s 0.5-pJ/b Encoding-Less Inductive Coupling Interface Achieving 111-GB/s/W 3D-Stacked SRAM in 7-nm FinFET,”
   IEEE Solid-State Circuits Letters (SSC-L), vol. 6, pp. 65-68, 2023.
   [DOI] 10.1109/LSSC.2023.3252607
6. R. Sumikawa, K. Shiba, A. Kosuge, M. Hamada, and T. Kuroda,
   “1.2-nJ/classification 2.4-mm² asynchronous wired-logic DNN processor using synthesized nonlinear function blocks in 0.18-µm CMOS,”
   JSAP Japanese Journal of Applied Physics (JJAP), vol. 62, no. SC, pp. SC1019, 2023.
   [DOI] 10.35848/1347-4065/acac38
7. S. Shibata, R. Miura, Y. Sawabe, K. Shiba, A. Kosuge, M. Hamada, and T. Kuroda,
   “A 5-GHz 0.15-mm² Collision-Avoiding RFID Employing Complementary Pass-transistor Adiabatic Logic with an Inductively Connected External Antenna in 0.18-μm CMOS,”
   IEEE Solid-State Circuits Letters (SSC-L), vol. 5, pp. 268-271, 2022.
   [DOI] 10.1109/LSSC.2022.3223079
8. R. Miura, S. Shibata, M. Usui, K. Shiba, A. Kosuge, M. Hamada, and T. Kuroda,
   “A bonding-less 5-GHz RFID module using inductive coupling between IC and antenna,”
   JSAP Japanese Journal of Applied Physics (JJAP), vol. 61, no. SC, pp. SC1058, 2022.
   [DOI] 10.35848/1347-4065/ac4ce2
9. K. Shiba, T. Omori, K. Ueyoshi, S. Takamaeda-Yamazaki, M. Motomura, M. Hamada, and T. Kuroda,
   “A 96-MB 3D-Stacked SRAM Using Inductive Coupling with 0.4-V Transmitter, Termination Scheme and 12:1 SerDes in 40-nm CMOS,”
   IEEE Transactions on Circuits and Systems-I: Regular Papers (TCAS-I), vol. 68, no. 2, pp. 692-703, Feb. 2021.
   [DOI] 10.1109/TCSI.2020.3037892
10. K. Shiba, T. Omori, M. Usui, M. Hamada, and T. Kuroda,
    “Area-Efficient Multihop Inductive Coupling Interface for 3D-Stacked Memory With 0.23-V Transmitter and Sub-10-μm Coil Design,”
    IEEE Solid-State Circuits Letters (SSC-L), vol. 3, pp. 370-373, 2020.
    [DOI] 10.1109/LSSC.2020.3022417
11. K. Shiba, C. Cheng, M. Hamada, and T. Kuroda,
    “2.5D integration using inductive-coupling TSV-less miniature interposer achieving 317 Gb/s/mm², 1.2 pJ/b data-transfer,”
    JSAP Japanese Journal of Applied Physics (JJAP), vol. 59, no. SG, pp. SGGL06, 2020.
    (Selected as Spotlights and Highlights of 2020)
    [DOI] 10.35848/1347-4065/ab70ab
12. K. Shiba, M. Hamada, and T. Kuroda,
    “3D system-on-a-chip design with through-silicon-via-less power supply using highly doped silicon via,”
    JSAP Japanese Journal of Applied Physics (JJAP), vol. 59, no. SG, pp. SGGL04, 2020.
    [DOI] 10.35848/1347-4065/ab7699

International Conference Presentation/国際会議発表

1. K. Shiba, Z. Zhan, K. Nii, Y. Wang, T.-Y. J. Chang, A. Kosuge, M. Hamada, and T. Kuroda,
   “A 28-nm 0.8M-weights/mm² 9.1-TOPS/mm² SRAM-Based All-Analog Compute-In-Memory Using Fine-Grained Structured Pruning with Adaptive-Ranging ADC,”
   IEEE European Solid-State Electronics Research Conference (ESSERC), pp. 365-368, Sep. 2024.
2. X. Wang, A. Kosuge, Y. Hayashi, K. Shiba, M. Hamada, and T. Kuroda,
   “Analysis and Design of a 7 Gb/s Rotatable Non-Contact Connector with Grid Array Package Application,”
   IEEE International New Circuits and Systems Conference (NEWCAS), June 2023.
3. A. Kosuge, R. Sumikawa, Y.-C. Hsu, K. Shiba, M. Hamada, and T. Kuroda,
   “183.4nJ/inference 152.8μW Single-Chip Fully Synthesizable Wired-Logic DNN Processor for Always-On 35 Voice Commands Recognition Application,”
   IEEE Symposium on VLSI Circuits, Dig. Tech. Papers, June 2023.
4. Y.-C. Hsu, A. Kosuge, R. Sumikawa, K. Shiba, M. Hamada, and T. Kuroda,
   “A Fully Synthesized 13.7μJ/prediction 88% Accuracy CIFAR-10 Single-Chip Data-Reusing Wired-Logic Processor Using Non-Linear Neural Network,”
   ACM Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 182-183, Jan. 2023.
   [DOI] 10.1145/3566097.3567942
5. R. Sumikawa, K. Shiba, A. Kosuge, M. Hamada, and T. Kuroda,
   “A 1.2nJ/Classification Fully Synthesized All-Digital Asynchronous Wired-Logic Processor Using Quantized Non-linear Function Blocks in 0.18µm CMOS,”
   ACM Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 180-181, Jan. 2023.
   [DOI] 10.1145/3566097.3567941
6. K. Shiba, M. Okada, A. Kosuge, M. Hamada, and T. Kuroda,
   “A 12.8-Gbps 0.5-pJ/b Encoding-less Inductive Coupling Interface Using Clocked Hysteresis Comparator for 3D-Stacked SRAM in 7-nm FinFET,”
   IEEE Asian Solid-State Circuits Conference (A-SSCC), Nov. 2022.
   [DOI] 10.1109/A-SSCC56115.2022.9980775
7. S. Shibata, Y. Sawabe, K. Shiba, A. Kosuge, M. Hamada, and T. Kuroda,
   “A Low-Power RFID with 100kbps Data Rate Employing High-Speed Power Clock Generator for Complementary Pass-Transistor Adiabatic Logic,”
   IEEE International Conference on Electronics Circuits and Systems (ICECS), Oct. 2022.
   [DOI] 10.1109/ICECS202256217.2022.9971064
8. R. Sumikawa, K. Shiba, A. Kosuge, M. Hamada, and T. Kuroda,
   “A 1.2nJ/Classification 2.4mm² Neuron Cell Array Using Logically Compressed Non-Linear Function Blocks in 0.18μm CMOS,”
   JSAP International Conference on Solid State Devices and Materials (SSDM), Sep. 2022.
9. S. Shibata, R. Miura, Y. Sawabe, K. Shiba, A. Kosuge, M. Hamada, and T. Kuroda,
   “A 5-GHz 0.15-mm² Collision Avoidable RFID Employing Complementary Pass-Transistor Adiabatic Logic with an Inductively Connected External Antenna (invited),”
   IEEE European Solid-State Circuits Conference (ESSCIRC), Sep. 2022.
10. K. Shiba, M. Okada, A. Kosuge, M. Hamada, and T. Kuroda,
    “A 7-nm FinFET 1.2-TB/s/mm² 3D-Stacked SRAM with an Inductive Coupling Interface Using Over-SRAM Coils and Manchester-Encoded Synchronous Transceivers,”
    IEEE Hot Chips 34 Symposium (HCS), Aug. 2022.
    [DOI] 10.1109/HCS55958.2022.9895622
11. Y.-C. Hsu, A. Kosuge, R. Sumikawa, K. Shiba, M. Hamada, and T. Kuroda,
    “A 13.7μJ/prediction 88% Accuracy CIFAR-10 Single-Chip Wired-logic Processor in 16-nm FPGA Using Non-Linear Neural Network,”
    IEEE Hot Chips 34 Symposium (HCS), Aug. 2022.
    [DOI] 10.1109/HCS55958.2022.9895600
12. K. Shiba, M. Okada, A. Kosuge, M. Hamada, and T. Kuroda,
    “Polyomino: A 3D-SRAM-Centric Architecture for Randomly Pruned Matrix Multiplication with Simple Rearrangement Algorithm and x0.37 Compression Format,”
    IEEE International New Circuits and Systems Conference (NEWCAS), June 2022.
    [DOI] 10.1109/NEWCAS52662.2022.9842091
13. K. Shiba, T. Omori, K. Ueyoshi, S. Takamaeda-Yamazaki, M. Motomura, M. Hamada, and T. Kuroda,
    “A 96-MB 3D-Stacked SRAM Using Inductive Coupling with 0.4-V Transmitter, Termination Scheme and 12:1 SerDes in 40-nm CMOS,”
    IEEE International Symposium on Circuits and Systems (ISCAS), May 2022.
14. T. Omori, K. Shiba, A. Kosuge, M. Hamada, and T. Kuroda,
    “A Physical Verification Methodology for 3D-ICs Using Inductive Coupling,”
    IEEE Electrical Design of Advanced Packaging and Systems (EDAPS), pp. 72-74, Dec. 2021.
    [DOI] 10.1109/EDAPS53774.2021.9657043
15. S. Shibata, R. Miura, Y. Sawabe, K. Shiba, A. Kosuge, M. Hamada, and T. Kuroda,
    “A 5-GHz 0.15-mm² Collision Avoidable RFID Employing Complementary Pass-Transistor Adiabatic Logic with an Inductively Connected External Antenna,”
    IEEE Asian Solid-State Circuits Conference (A-SSCC), Nov. 2021.
    [DOI] 10.1109/A-SSCC53895.2021.9634815
16. K. Shiba, T. Omori, M. Hamada, and T. Kuroda,
    “Area-Efficient Multi-Hop Inductive Coupling Interface for 3D-Stacked Memory with 0.23-V Transmitter and Sub-10-μm Coil Design,”
    IEEE European Solid-State Circuits Conference (ESSCIRC), Sep. 2021.
17. R. Miura, S. Shibata, M. Usui, K. Shiba, A. Kosuge, M. Hamada, and T. Kuroda,
    “A bonding-less 5-GHz RFID module using a 300um x 500um IC chip,”
    JSAP International Conference on Solid State Devices and Materials (SSDM), pp. 686-687, Sep. 2021.
18. T. Omori, K. Shiba, M. Hamada, and T. Kuroda,
    “Sub-10-μm Coil Design for Multi-Hop Inductive Coupling Interface,”
    ACM Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 99-100, Jan. 2021.
    [DOI] 10.1145/3394885.3431649
19. K. Shiba, T. Omori, M. Hamada, and T. Kuroda,
    “A 3D-Stacked SRAM Using Inductive Coupling Technology for AI Inference Accelerator in 40-nm CMOS,”
    ACM Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 97-98, Jan. 2021.
    [DOI] 10.1145/3394885.3431642
20. K. Shiba, T. Omori, M. Okada, M. Hamada, and T. Kuroda,
    “Crosstalk Analysis and Countermeasures of High-Density Multi-Hop Inductive Coupling Interface for 3D-Stacked Memory,”
    IEEE Electrical Design of Advanced Packaging and Systems (EDAPS), pp. 37-39, Dec. 2020.
    [DOI] 10.1109/EDAPS50281.2020.9312890
21. K. Ando, K. Shiba, K. Akatsuka, C. Cheng, T. Arakawa, M. Hamada, and T. Kuroda,
    “A 50 Mbps/pin 12-input/output 40 nsec Latency Wireless Connector Using a Transmission Line Coupler with Compact SERDES IC in 180 nm CMOS,”
    IEEE International Conference on Electronics Circuits and Systems (ICECS), Nov. 2020.
    (Selected as Best Student Paper Award)
    [DOI] 10.1109/ICECS49266.2020.9294868
22. K. Shiba, T. Omori, K. Ueyoshi, K. Ando, K. Hirose, S. Takamaeda-Yamazaki, M. Motomura, M. Hamada, and T. Kuroda,
    “A 3D-Stacked SRAM Using Inductive Coupling with Low-Voltage Transmitter and 12:1 SerDes,”
    IEEE International Symposium on Circuits and Systems (ISCAS), Oct. 2020.
    [DOI] 10.1109/ISCAS45731.2020.9181008
23. M. Usui, K. Shiba, M. Hamada, and T. Kuroda,
    “3D Integration of Ka-band RFIC by Inductive Inter-chip Wireless Communication Using Figure-8 Coils,”
    IEEE Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS), Oct. 2020.
    [DOI] 10.1109/EPEPS48591.2020.9231390
24. C. Cheng, K. Shiba, M. Hamada, and T. Kuroda,
    “2.5D Integration Using Inductive-Coupling TSV-less Miniature Interposer Achieving 317Gb/s/mm², 1.2pJ/b Data Transfer,”
    JSAP International Conference on Solid State Devices and Materials (SSDM), pp. 517-518, Sep. 2019.
25. K. Shiba, M. Hamada, and T. Kuroda,
    “3D SoC Design with TSV-less Power Supply Employing Highly Doped Silicon Via,”
    JSAP International Conference on Solid State Devices and Materials (SSDM), pp. 515-516, Sep. 2019.

Domestic Conference Presentation/国内会議発表

1. 柴康太, 宮田知輝, 門本淳一郎, 天野英晴, 黒田忠広,
   “ThruChip Interfaceの設計自動化,”
   情報処理学会 全国大会, Mar. 2018.

Invited Lecture/招待講演

1. 柴康太, 小菅敦丈, 濱田基嗣, 黒田忠広,
   “[招待講演] 三次元積層SRAMと近接場無線接続技術,”
   電子情報通信学会(IEICE) 集積回路研究会(ICD) メモリ技術と集積回路技術一般, Apr. 2022.

和文解説記事

1. 柴康太, 小菅敦丈, 濱田基嗣, 黒田忠広,
   “近接場無線接続技術を用いた三次元積層SRAM,”
   エレクトロニクス実装学会誌, vol. 25, no. 6, pp. 549-555, Sep. 2022.
   [DOI] 10.5104/jiep.25.549

Award/受賞

1. IEEE Solid-State Circuits Society (SSCS) Pre-Doctoral Achievement Award, 2023.
2. Best Student Paper Award, IEEE International Conference on Electronics Circuits and Systems (ICECS), Nov. 2020. (Co-recipient)
3. IEEJ Tokyo Branch Student Encouragement Award, The Institute of Electrical Engineers of Japan, Mar. 2018.

Scholarship/奨学金

1. The University of Tokyo Toyota-Dwango Scholarship for Advanced AI Talents (東京大学トヨタ・ドワンゴ高度人工知能人材奨学金), 東京大学, Apr. 2021 – Mar. 2022.
2. Japan Student Services Organization Scholarship (Repayment Fully Exempted), Japan Student Services Organization, Arp. 2020 – Mar. 2021.
3. Nagoya-Mitakai Scholarship (名古屋三田会奨学基金), 慶應義塾大学, Apr. 2018 – Mar. 2019.

Graduate Thesis/学位論文

• K. Shiba, “Low-power High-bandwidth 3D-stacked SRAM Using Inductive Coupling,” The University of Tokyo Ph.D. Dessertation, Mar. 2023.
• K. Shiba, “A 3D-Stacked Memory Using Inductive Coupling Multi-Hop with Sub-10-μm Coils and Low-Voltage Transmitter,” Keio University Master’s Thesis, Mar. 2020.
• K. Shiba, “Design Automation of ThruChip Interface 2.5D,” Keio University Bachelor’s Thesis, Mar. 2018.

Funding/競争的資金

1. K. Shiba, “積層型AIチップの低電力高効率アーキテクチャ,” JST ACT-X Grant Number JPMJAX210A, Oct. 2021 – Mar. 2023.
2. K. Shiba, “TSVレス三次元積層SRAM,” JSPS KAKENHI Grant Number 21J11729, Apr. 2021 – Mar. 2023.

Media Appearances/メディア報道

1. “東大など、従来より3桁以上消費電力が少ないAIプロセッサを開発,”
   マイナビTECH+, 2023年6月12日.
2. ”半導体復活のチャンスをオープンとクローズの両戦略で生かす。,”
   テレスコープマガジン, 2021年5月7日.